UNITES Systems a.s.
Kpt. Macha 1372
757 01 Valašské Meziříčí
T: 571 757 230
E: info@unites.cz
IČ: 25863665   DIČ: CZ25863665

Kontakty

TA17B - Procesory a periferie, paměti, logické obvody, TTL

TA17B - Procesory a periferie, paměti, logické obvody, TTL

Testuje: Procesory a periferie, paměti, logické obvody, TTL 

TEST GROUPS ARCHITECTURE

  • 48 bidirectional test signals
  • Data rate up to 10 MHz
  • Hardware test evaluating in the input mode
  • Expected data stored in the output channel
  • Input data compared with the expected data
  • Fail marks of the input vectors stored
  • 10-bit fail events counter

Parameters

  • Parameter - Group 0 - Groups 1 .. 5
  • Signals Number
    • 8 bidirectional
  • Pattern Out Depth
    • 2048 (Standard) 
    • 32768 (max)
  • Pattern In Depth
    • 2048 (Standard) 
    • 32768 (max)
  • Direction Control
    • single (In or Out)
      • common (In or Out)
  • Output Timing
    • single (Start/Stop)
      • common (Start/Stop)
  • Input Timing common (Load Point)
  • Format Control common
  • Output Format *
    • return-to-zero 
    • return-to-one 
    • surround-by-complement 
    • non-return
  • Input Format
    • data 
      • data 
      • fail marks 
      • fail number (0..65535)
  • FIFO Unit Control
    • Reset and Retransmit
  • FIFO Unit Flags
    • Empty and Full
  • Synchronization
    • independent In and Out
  • Output Low Level
    • 0.3 V .. 5.5 V
  • Output High Level
    • 0.3 V .. 5.5 V
  • Input Threshold
    • 0.3 V .. 5.5 V
  • Timing Range
    • 255 ns or 1275 ns

„*“ for all pins in the group

Nahoru